The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device which can lessen step formation due to unwanted losses of an isolation layer and thereby stabilize the characteristics of a gate insulation layer.
Generally gate insulation layers in semiconductor devices are grown through annealing or rapid thermal annealing processes that produce a silicon oxide layer (an SiO2 layer). As the design rules demand more diminutive semiconductor devices, the thickness of the gate insulation layer is reduced down to a thickness level that defines a tunneling limit.
Due to the refresh characteristics of transistors in a cell region, the transistors in the cell region require a higher threshold voltage (Vt) than transistors in a peripheral region. Hence, a relatively higher voltage is applied to the transistors in the cell region, as a result of which the electrical performance of the transistors in the cell region are degraded as compared to those transistors in the peripheral region.
Under these circumstances, in order to prevent the electrical performance of the transistors in the cell region from being degraded, a method of forming a dual gate insulation layer has been proposed. This method results in forming a thicker gate insulation layer of transistors in a cell region relatively to that in a peripheral region.
However, in the conventional method for forming a dual gate insulation layer, when conducting a wet etching process for selectively removing the gate insulation layer in the peripheral region, not only the gate insulation layer in the peripheral region is removed, but also unwanted losses to the isolation layer result in a step portion when formed between an active region and the isolation layer.
In order to accommodate the trend toward high integration of a semiconductor device, an SOD (spin-on dielectric) insulation layer is used which provides excellent gapfill characteristics when formed in an isolation trench that has an increased aspect ratio. Unfortunately, the resultant SOD insulation layer exhibits unwanted characteristics in that the SOD insulation layer is prone to being easily etched when conducting wet etching processes. As a result, losses of the isolation layer markedly increase and the thickness of a step portion increases up to 350 Å.
If the step portion is formed between the active region and the isolation layer due to the loss of the isolation layer, then the characteristics of the gate insulation layer become unstable. Furthermore, residues are created on the step portion when subsequently conducting a masking process and an etching process for forming gates. Because of these facts, defects are likely to occur in a semiconductor substrate and the performance characteristics and reliability of a semiconductor device can deteriorate.